Designers of digital to analog converters (DACs) face several challenges today. One such challenge presents itself when attempting to perform digital to analog conversion using the well-known pulse-width modulation technique. FIG. 1 is a simplified schematic of a pulse-width modulation (PWM) DAC.
The challenge facing DAC designers attempting to use PWM DACs is providing a desired number of voltage steps within the constraints of the filters that are currently practically available.
FIG. 1 is a simplified block diagram of a PWM DAC 100. Digital input values 102 to be converted to an analog amplitude output 104 are stored in a Pulse Width Register 106. A Max Value Register 108 is loaded with a terminal or maximum value. The maximum value109 is loaded into a reloadable counter 110. The reloadable counter 110 generates a ramp signal output 112 at a rate determine by a signal output from a clock 111. That is, the digital value output from the counter 110 will increase linearly from a starting value to the maximum value 109 stored in the Max Value Register 108.
FIG. 2 is an illustration of the waveforms created by the PWM DAC 100. When the value 112 output from the counter 110 reaches the maximum value 109, the counter output value 112 returns to the starting value 204 (typically zero). Referring back to FIG. 1, the output 112 from the counter 110 is coupled to a comparator 114. The comparator 114 compares the value 112 output from the counter 110 to the value 116 output from a Pulse Width Register 106. When the value 112 of the ramping signal output from the counter 110 is less than the value 116 in the Pulse Width Register 106, the output 118 of the comparator 114 is high.
At the point 206 where the value of the ramping signal 112 output from the counter 110 crosses the value held in the Pulse Width Register 106, the comparator output 118 goes low. The correlation between the point 206 and the state of the output 118 is illustrated by a dashed line 208, It can be seen from FIG. 2 that by moving the value 116 up, the pulse width of the output 118 (i.e., the amount of time the pulse is high) will increase. By moving the value 116 down, the pulse width of the output 118 will decrease. That is, the crossing point 206 moves to the left as the value 116 goes down and moves to the right as the value 116 goes up.
It can be seen from FIG. 2 that the output 109 of the Max Value Register 108 sets the length of a cycle (i.e., the distance between rising edges of the output 118). The output 118 of the comparator 114 is then applied to a filter 120. The filter 120 integrates the output 118 to create a signal with an amplitude that is proportional to the value loaded into the Pulse Width Register 106. Thus, the circuit acts as a DAC that converts the digital input signal 102 to an analog output signal 104.
It should be noted that the duty cycle of the output 118 is 50% when the value of the input signal 102 is midway between the maximum and minimum values. Therefore, the maximum power resides at a frequency determined by the Max Value Register 108 and the frequency of the clock 111. It should also be noted that this is the lowest frequency generated in the spectrum of the output 118. That means that filter 120 has to be efficient at the low end of the spectrum in order to perform well. This poses challenges for the design of the DAC. This is even more difficult when there is a desire to have a large number of voltage steps. That is, when the number of bits in the Pulse Width Register 106 is high (i.e., the resolution of the PWM is high), the frequencies that must be passed include relatively high frequencies as the value of the Pulse Width Register 106 approaches the maximum value or the minimum value.
One way to mitigate the difficulties in making a filter suited to the task is to shift the relationship between the frequency of the output 118 and the amplitude of the digital input signal (i.e., the magnitude of the value stored in the Pulse Width Register 106). One way to shift this relationship is to use a pulse density modulation (PDM) DAC.
FIG. 3 is a simplified schematic of a PDM DAC 300. The PDM DAC 300 works in a manner similar to that of the PWM DAC 100. However, the output port 312 of the counter 310 is coupled to a bit reversal module 313. The bit reversal module outputs a value 315 that is a mirror image of the input value 312. The output of the counter 310 is synchronized by a clock signal 311 from a clock 317.
FIG. 4 illustrates the bit reversal for one set of example values 312, 315. The least significant bit (LSB) D0 is swapped with the most significant bit (MSB) D7. The next least significant bit D1 is swapped with the next most significant bit D6. This continues for each of the 8 bits shown in FIG. 4. Accordingly, the value of 312 read from left to right is equal to the bit reversed value of 315 when read from right to left. Such bit reversal can be accomplished by a last-in, first-out register.
FIG. 5 is an illustration of the output 315 of the bit reversal module 313 and the output 318 of the comparator 314. The pattern created at the output 315 of the bit reversal module 313 causes the output 315 to oscillate between values in a pattern that repeats when the counter 310 reaches the max value 309. The output 315 of the bit reversal module 313 is compared with the output 316 of a Pulse Density Register 306. A first dashed line 503 represents the minimum value that the output 316 of the Pulse Density Register 306 can take. A second dashed line 505 represents the maximum value that the output 316 of the Pulse Density Register 306 can take.
A horizontal line 507 is shown in FIG. 5 to represent a value output from the Pulse Density Register 306 that is approximately mid-range between the maximum value 505 and the minimum value 503. It can be seen from the plot of the output 315 of the bit reversal module 313 that as the value in the Pulse Density Register 306 increases from the mid-range value 507 to the maximum value 505, the number of times the output 315 of the bit reversal module 313 crosses the value output by the Pulse Density Register 306 decreases. Likewise, as the value decreases from the mid-range value 507, the number of times the output 315 of the bit reversal module 313 crosses the value decreases. Therefore, the output 318 will have the highest pulse density (and so a higher frequency in the frequency domain) at values closest to mid-range. The frequency will decrease as the pulse density value 316 increases or decreases from mid-range.
Using the PDM DAC 300 rather than the PWM DAC 100 results in an output for which it is easier to design a filter. However, the comparator output 318 will be a relatively consistent stream of pulses for most values stored in the Pulse Density Register 306. Such consistent streams of pulses can cause interference with other nearby circuits.
Accordingly, there is presently a need for an ADC that can convert digital signals to analog signals, both without requiring a filter that is difficult to design and without generating pulse streams that can interfere with other circuits.